The present invention relates to a data processor for controlling a serial communication.
A serial communication control unit (serial communication control means) for such a data processor activates a ready signal upon completion of a cycle of data transmission or reception and requests other units for data processing, such as writing the next transmitting data or reading the received data. These data processes are divided into two methods; a process by interrupt and a process by direct memory access (DMA) transfer.
The transfer process by interrupt is carried out as follows. The serial communication control unit activates a ready signal upon completion of a cycle of data transmission or reception and transmits it to a central processing unit (CPU) via an interrupt control unit. Upon reception of the ready signal as an interrupt request from the serial communication control unit, the CPU saves the internal conditions and determines the interrupt process routine to be executed for starting the execution.
The interrupt process routine checks the conditions of the serial communication control unit and, if transmission is completed, writes data for the next data transmission to the serial communication control unit and, if reception is completed, reads the received data from the serial communication control unit. The above process which is carried out whenever the serial communication control unit transmits or receive a piece of data is repeated until all data is transferred. Thus, the unit of process carried out by the CPU is the transfer of a piece of data. Whenever the serial communication control unit transfers a piece of data, an interrupt is applied to the CPU to process the transferred data.
A conventional data processor using such interrupts, which is described in Japanese Patent Application Kokai No. 62-75857, is shown in FIG. 4. It includes a central processing unit (CPU) 11 for processing data, a system bus 12, a serial interface circuit 13 for serial communication control, a buffer 14 for transmission and reception, and an interrupt controller 15 for controlling interrupts. The process by this data processor is the same as the above process by interrupt and its description is omitted.
In addition to the process by interrupt wherein the unit of process carried out by the CPU is the transfer of a piece of data carried out by the serial communication control unit, there is another process or process by DMA transfer wherein the CPU does not process any data until a group of pieces of data is transferred. This process by DMA transfer is described below.
First of all, it is assumed that the DMA control unit (DMA control means) has a transfer unit and that the main memory has a buffer memory area for storing the transfer data. When the serial communication control unit completes a data transfer, a ready signal is activated and transmitted to the DMA control unit (DMA control means). Taking reception for example, upon reception of the ready signal as a DMA transfer request from the serial communication control unit, the DMA control unit carries out by DMA transfer reading the received data from the serial communication control unit, which has completed the transfer, and writing the data in the buffer memory area which has been held. The DMA transfer between the serial communication control unit and the buffer memory area is repeated until all data is transferred. Upon completion of the transfer completion interrupt to the CPU indicating completion of the serial communication transfer. Upon reception of the interrupt, the CPU carries out a process for processing the interrupt and starts processing the interrupt to carry out a programmed process for all the data stored in the buffer memory area.
In this way, in the process by DMA transfer, a block of data to be transmitted or received by the serial communication control unit is stored in a buffer memory area by DMA transfer, and the CPU processes it at once when all the data of the serial communications is transferred.
A conventional data processor for carrying out such a process by DMA transfer, which is described in Japanese Patent Application Kokai No. 62-75857, is shown in FIG. 5. It includes a central processing unit (CPU) 11, a system bus 12, a serial interface circuit 13 for serial communication control, an interrupt controller 15 for controlling interrupts, a receiving buffer 16, a transmitting buffer 17 (the receiving buffer 16 and the transmitting buffer 17 constituting a memory unit 18), a direct memory access controller (DMAC) 19 as DMA control means, a data comparator 20, and a local data bus 21.
The process by DMA transfer by this data processor is the same as described above, and its description is omitted.
In the data processor of FIG. 5, the ready signal from the serial communication control unit is hard wired to the DMA control unit as a DMA transfer request so that it is possible to use only the process by DMA transfer in the serial communication data processing. In the data processor with a serial communication control unit of FIG. 4, on the other hand, the ready signal from the serial communication control unit is hard wired to the interrupt control unit as an interrupt request line so that it is possible to use only the process by interrupt in the serial communication data processing.